LT3500
12
3500fc
APPLICATIONS INFORMATION
Table 1. Ef ciency and Size Comparisons for Different R
RT/SYNC
Values, V
OUT1
= 3.3V
FREQUENCY
R
T
/SYNC
EFFICIENCY
V
IN(MAX)
L
C
C + L AREA
(mm
2
)
2.5MHz
15k
73.6
12
1?/DIV>
10?/DIV>
24
2.0MHz
20k
81.5
14
1.5?/DIV>
10?/DIV>
24
1.5MHz
24.9k
84.5
18
2.2?/DIV>
10?/DIV>
24
1.0MHz
40.2k
87.3
28
3.3?/DIV>
22?/DIV>
34
500kHz
90.9k
88.9
36
4.7?/DIV>
47?/DIV>
40
The following example along with the data in Table 1
illustrates the tradeoffs of switch frequency selection.
Example.
V
IN
= 25V, V
OUT1
= 3.3V, I
OUT1
= 2.0A,
Temperature = 0癈 to 85癈
t
ON(MIN)
= 185ns (85癈 from Typical Characteris-
tics graph), V
D
= 0.6V, V
SW
= 0.4V (85癈)
Max Frequency=
3.3+0.6
250.4+0.6
"
1
185ns
~835kHz
R
T
/SYNC ~ 49.9k
Frequency E 820kHz
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined.
The minimum input voltage is determined by either the
LT3500s minimum operating voltage of ~2.8V or by its
maximum duty cycle. The duty cycle is the fraction of time
that the internal switch is on during a clock cycle. The
maximum duty cycle can be determined from the clock
frequency and the minimum off time from the typical
characteristics graph.
This leads to a minimum input voltage of:
V
IN(MIN)
=
V
OUT1
+V
D
DC
MAX
V
D
+V
SW
where V
SW
is the voltage drop of the internal switch,
and
DC
MAX
= 1 t
OFF(MIN)
" Frequency.
Figure 3 shows a typical graph of minimum input voltage
vs load current for 3.3V and 5V applications.
The maximum input voltage is determined by the absolute
maximum ratings of the V
IN
and BST pins and by the
frequency and minimum duty cycle.
The minimum duty cycle is de ned as:
DC
MIN
= t
ON(MIN)
" Frequency
Maximum input voltage as:
V
IN(MAX)
=
V
OUT1
+V
D
DC
MIN
V
D
+V
SW
Figure 3. Minimum Input Voltage vs Load Current
LOAD CURRENT (A)
0
3
4
5
1.0
1.6 1.8
3500 F03
2
0.2 0.4 0.6 0.8
1.4
1.2
6
7
8
2.0
V
OUT1
= 5V START-UP
V
OUT1
= 5V RUNNING
V
OUT1
= 3.3V START-UP
V
OUT1
= 3.3V RUNNING
f
SW
= 1MHz
L = 3.3糎
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